The present invention relates generally to circuits for controlling sequential machines and relates more specifically to variable speed, synchronous, digital clocks.
Most sequential machines are controlled by clocks having a period which is fixed for each function to be performed. The normal design practice is to select a clock period sufficient for execution time using the worst case input conditions. This means that the function is performed at a fixed speed. This is particularly disadvantageous for machines having variable length operands. Either the length of operands must be limited to a narrow range or each execution of a function must proceed at no faster than the worst case execution time.